Examples of prior art wherein data streams of a number of types greater than the number of DMA channels are transferred are disclosed in the specifications of Japanese Patent Application Laid-Open (KOKAI) Nos. JP-A-62-79558, 64-59445 and 2-278361.
In DMA transfer according to the prior art set forth in these specifications, one DMA request signal output from each of a number of data processors which issue DMA requests and one DMA acknowledge signal sent to the data processor are validated so that DMA requests of a number greater than the actual number of DMA channels can be processed.
For example, the specification of Japanese Patent Application Laid-Open JP-A-62-79558 proposes a DMA controller arrangement in which data transfer by a large number of channels is made possible by externally connecting distributing circuits which distribute outputs to any one of a plurality of different peripheral devices, with the number of distributing circuits conforming to the requisite number of channels. More specifically, as shown in FIG. 8, one set of DMA request signals is selected by a DMA request signal selecting circuit 82 based upon a control signal Co, one DMA acknowledge signal is selected from several DMA acknowledge signals based upon the same control signal Co, and processing of DMA requests of a number greater than the number of channels of a DMA controller 81 is executed.
Further, the specification of Japanese Patent Application Laid-Open JP-A-64-59445 discloses DMA transfer control in an adapter designed so as to be capable of processing data requests from a plurality of requesters using a DMA controller having one channel. As shown in FIG. 9, one set of DMA request signals and DMA acknowledge signals is selected by a DREQ arbiter controller 96 from several DMA request signals and DMA acknowledge signals, and processing of DMA requests of a number greater than the number of channels of the DMA controller is executed. That is, data transfer requests DREQ(a), (b), (c), (d) from many requesters are entered into a DMA controller DMAC 95 as one DREQ by the DREQ arbiter controller 96, and ID information is utilized upon being added onto data or an address. For example, at the time of a DMA transfer from an input/output unit to a memory, ID information from the DREQ arbiter controller 96 is written to a local memory 93 via a multiplexer MPX 97 in an initial cycle, and DMA data from a requester that has been selected by the DREQ arbiter controller 96 is written to the local memory 93 via the multiplexer 97 in the next cycle.
As shown in FIG. 10, the specification of Japanese Patent Application Laid-Open JP-A-2-278361 discloses an arrangement in which DMA request input terminals 115 in a DMA controller are equipped with a multiplexer 112 and DMA acknowledge output terminals 116 are equipped with a demultiplexer 113, thereby making it possible to connect a large number of DMA transfer requesting devices while suppressing an increase in the amount of hardware within the DMA controller. One set of DMA request signals and DMA acknowledge signals is selected based upon a value stored in a selection register 114 and processing of DMA requests of a number greater than the number of channels of a DMA controller is executed.